Get an overview of Veridise’s ZK tools and a glimpse into what’s next. @IsilDillig shares our future directions at the @a16zcrypto event. https://t.co/QlZNSm3ITO

Our ZK detection tools previously timed out on 30% of ZK circuits. How did we solve this? @IsilDillig shares insights from our recent research paper. https://t.co/88VIf6mm8j

How do we keep ZK circuits rock-solid and deterministic during audits? Our co-founder @IsilDillig shares insights on combining static analysis and SMT solvers in our ZK tools. https://t.co/rJzdJJm9pE

Under-constrained circuits are the most common source of ZK circuit vulnerabilities. What does this really mean in technical terms? @IsilDillig shares. https://t.co/I1PVsZgdod

What happens if your ZK circuit has a bug? What does an incorrect ZK circuit even mean? Our co-founder @IsilDillig explores these critical questions from a formal methods perspective at the @a16zcrypto event. https://t.co/4mZbLcguLL

Check out the blog post summary of @IsilDillig's presentation at @a16zcrypto here:Formal Methods for Zero-Knowledge Circuitshttps://t.co/aiJozDkXww https://t.co/J4NgXiJuyJ

Our co-founder @IsilDillig took the stage at an @a16zcrypto event to deliver a comprehensive presentation on Formal Methods for Zero-Knowledge Circuits. See the full recording and a summary below 🧵 1/4 https://t.co/ZsJlPuPE7q